Rama Karedla

Programming for the Intel Xeon Processor 02-27-2015 @ 3:45 - 4:45

Rama Karedla — Rama Karedla works as a Performance Architect at Intel and supports the Financial Services vertical. He works with various financial customers to help optimize their applications on Intel Architectures and acts as a conduit, providing feedback on customer requirements, to Intel Architects. His current interests include programming for Low latency and optimizing for big data and the cloud. Rama started his career with Digital working on Distributed systems and Hierarchical Storage Management and published an ACM paper on caching in storage systems. He later worked for IBM on Domino performance prior to accepting a position at Intel. At some point he plans to go back to research in music perception.

Software programmers tend to focus on the software layer leaving performance on the table by not taking advantage of the underlying hardware. This talk will help the programmer take advantage of the underlying Intel Xeon server architecture to write more efficient programs. We broadly cover topics such as time measurement, memory ordering, making efficient use of the multi level caches, NUMA aware programming and the use of the many compute cores available in the Xeon architecture via multi-threading.

We hope to show the benefit to both, latency and throughput oriented applications. The talk will also address using the new AVX vector registers to achieve higher performance, and briefly touch upon the recently announced Transactional Synchronization Extensions (TSX) features. Examples of application profiling will demonstrate the benefit of optimizing for performance in parallel with code development.

Video (57:55)

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